Stereo demodulator circuit

ABSTRACT

A stereo demodulator circuit comprising at least one noise control unit for performing a noise control responding to an RSSI (reception electric-field intensity) when the RSSI is within a specified range, further comprises an AD converter unit for AD-converting a signal corresponding to the RSSI and a control signal producing unit for producing a control signal for a noise control performed in the noise control unit according to a noise level when the noise level obtained by the AD conversion is within the above described specified range. The control signal producing unit comprises an offset unit for digitally offsetting a signal obtained through the above described AD conversion by a predefined value and truncating lower bits off the offset value by the number of bits in compliance with a grade of the noise control accuracy and outputs the control signal based on the signal obtained from the offset unit.

TECHNICAL FIELD

The present invention relates to a stereo demodulator circuit used for astereo receiver, etc., particularly to an improvement of controltechnology applied to a series of circuits for a noise control equippedin the stereo demodulator circuit and further to the overall signalprocessing circuits including such a stereo demodulator circuit.

BACKGROUND ART

A stereo demodulator circuit generally is a circuit generating the L andR signals based on a received RF (Radio Frequency) signal.

In such a stereo demodulator circuit, an IF (Intermediate Frequency)signal is gained by converting the frequency of a received RF signal ina frequency conversion circuit, the IF signal is amplified by alimiter/amplifier and further detected by an FM detection circuit, andthereby a composite signal is reproduced.

The reproduced composite signal, generally including a main component,L+R, and a side component, L−R, is diverged into two paths. That is,from the composite signal a component, L+R, is gained in one path whilethe other component, L−R, is obtained by mixing with a 38 kHz signal forexample in the other path. From thus obtained components, i.e., L+R andL−R, the L signal and R signal are obtained by adding and subtracting,respectively, by using an adder/subtracter.

Additionally included sometimes is a noise control unit for attenuatingsignals and cutting high frequencies off signals in such a stereodemodulator circuit in order to suppress noise produced in the circuititself and thereby improve a sound quality.

An example of the above is a high-cut control (hereinafter called “HCC”)performed in response to a reception electric-field intensity(hereinafter called “RSSI”) signal by equipping a HCC circuit configuredfor mixing the above described component, L+R, with a signal which highfrequencies are cut off the component, L+R, in a mixing ratio respondingto an RSSI signal which is a signal indicating the RSSI. Another exampleis a high-cut control in which a high frequency noise included in the Land R components in the above stereo-modulated signal is cut in ade-emphasis circuit.

Meanwhile, also known is a soft muting processing in which the abovedescribed composite signal is attenuated in a soft muting (hereinaftercalled “SMUTE”) circuit when the RSSI is small so that the effect of amixed-in noise cannot be ignored.

Furthermore, also known is an adjustment of the mixing ratio of the maincomponent, L+R, to the side component, L−R, blended by theadder/subtracter in order to suppress a cross-talk. That is, the sidecomponent, L−R, is attenuated by a stereo noise control (hereinaftercalled “SNC”) in an SNC circuit.

A relationship between the above described RSSI and a controlledvariable in the respective circuit for performing the above describedHCC, SMUTE and SNC processing is determined as exemplified by FIG. 1.

In FIG. 1, for example, the HCC processing is performed by the controlsignal C₂˜C₃ responding to the actual RSSI if the RSSI is within therange I₂˜I₃. Note that the control signal is kept at C₂ if the RSSI issmaller than the minimum value I₂ within the range, while the controlsignal is kept at C₃ if the RSSI is larger than the maximum value I₃within the range.

Likewise, the SMUTE processing is performed by the control signal C₀˜C₁responding to the actual RSSI if the RSSI is within I₀˜I₁; and the SNCprocessing is performed by the control signal C₄˜C₅ responding to theactual RSSI if the RSSI is within I₄˜I₅. The control signal is likewisekept at the constant values if the RSSI is outside of the respectiverange, the same as performing the HCC processing above.

In the above described stereo demodulator circuit, since each of theHCC, SNC and SMUTE processing is an analog control, there has been aproblem of an accurate noise control being difficult due to aninherently unstable control operation.

Additionally, as the base voltage (i.e., bias voltage), i.e., the basisfor generating a control signal determining a noise control variable ineach of the HCC, SNC and SMUTE circuits, fluctuates caused by theambient temperature changes or the processing variations, it has beendifficult to continuously maintain the required bias voltage. In aconventional circuit (i.e., a differential amplifier circuit) appliedwith anon-zero bias, a predefined, non-zero bias (i.e., non-zero bias)is applied as the base voltage at the point, “a”, i.e., the input pointfor the base voltage, as exemplified by FIG. 2, and when the input valueVin which responds to the above described RSSI exceeds the abovedescribed base voltage (a predefined value), the difference of the twois amplified and outputted to each of the above described noise controlcircuits as the control signal.

Such configuration has been faced with problems such as the abovedescribed predefined bias value fluctuating caused by the temperaturechanges, processing variations, etc., resulting in a non-achievabilityof accurate noise control. In other words, a noise control processing bythe above described HCC, SNC or SMUTE ends up with performing for theRSSI being out of the proper operating range, hence making a cause forthe sound quality degradation.

DISCLOSURE OF INVENTION

Consequently, the primary object of the present invention is to enable astabilization of noise control performed by a noise control unit in astereo demodulator circuit comprising at least one noise control unitfor performing a noise control responding to a reception electric-fieldintensity when the reception electric-field intensity is within aspecified range and contrive a simpler configuration of a control signalproducing circuit for outputting a control signal for defining a controlvariable of the noise control.

The secondary object of the present invention is to make the abovedescribed noise control unit perform accurately, being unaffected by thetemperature changes or variations of the processing.

In order to achieve the above described objects, the present inventioncomprises as follows.

First, a stereo demodulator circuit according to a first aspect of thepresent invention is a stereo demodulator circuit comprising at leastone noise control unit for performing a noise control responding to areception electric-field intensity when the reception electric-fieldintensity is within a specified range, and further comprising an ADconverter unit for AD-converting a reception electric-field intensitysignal indicating the reception electric-field intensity; an offset unitfor digitally offsetting a digital signal obtained from the AD converterunit by a predefined value (e.g., a value according to the lowest valuein the specified range) according to the specified range and truncatinglower bits off the digital signal by the number of bits specified incompliance with a grade of noise control accuracy performed in the noisecontrol unit; and a control signal output unit for outputting a controlsignal defining a control variable of a noise control performed in thenoise control unit based on a signal obtained from the offset unit.

This configuration generates a control signal for defining a controlvariable for the noise control unit through a digital processing andthereby enables a significant stabilization of noise control operationsas compared to a conventional method of generating a control signalthrough an analog processing.

Meanwhile, the offset unit is configured so as not only to digitallyoffset a digital signal obtained by an AD-conversion, but also totruncate lower bits off the digital signal by the number of bits incompliance with a grade of noise control accuracy performed in the noisecontrol unit and generate a control signal in the control signal outputunit based on the remaining bits. Therefore, a signal processing in thecontrol signal output unit merely deals with a smaller number of bits incompliance with a grade of noise control accuracy as compared to a caseof generating a control signal by using the number of bits of a signalobtained by an AD-conversion as is, thereby enabling an efficient signalprocessing. As a result, it is possible to configure a substantiallysimpler circuit constituting the control signal output unit. Note herethat either the offsetting or the truncation of the lower bits can beprocessed first in the above contrivance.

Meanwhile, the noise control unit may be configured so as to be switchedstepwise for providing a noise control variable responding to a controlsignal outputted from the control signal output unit. Suchconfigurations, for example, include switching a plurality of switchesresponding to the above control signal and thereby increase or decreasethe noise control variables stepwise.

Although the AD converter unit can actually be configured by a common ADconversion circuit, a configuration comprising a latch circuit forretaining a signal obtained by the AD conversion circuit is also in thescope of the present invention.

Second, a stereo demodulator circuit according to a second aspect of thepresent invention is a stereo demodulator circuit comprising at leastone noise control unit for performing a prescribed control responding toa reception electric-field intensity when the reception electric-fieldintensity is within a specified range, and further comprising an offsetunit for offsetting a reception electric-field intensity signal which isa signal indicating the reception electric-field intensity by aspecified value (e.g., a value according to the lowest value in thespecified range) according to the specified range; a difference outputunit for comparing a signal obtained from the offset unit with a zerobias and outputting the resultant difference; and a control signaloutput unit for outputting a control signal defining a control variableof the control performed in the noise control unit based on a signalobtained from the difference output unit.

In such configuration, the offset unit actually offsets a receptionelectric-field intensity signal in advance, followed by the differenceoutput unit comparing with the zero bias and outputting the resultantdifference. Such configuration thus makes the basis for the comparisondone in the difference output unit being the zero bias, and therebyenables an accurate noise control performed in the noise control unitbeing unaffected by the above described temperature changes, processingvariations, etc.

Meanwhile, the present invention may be applied to a configurationhaving a plurality of noise control units in which case the specifiedrange of reception electric-field intensity is respectively specifiedfor each of the plurality of noise control units. The noise controlunits include, for example, a de-emphasis circuit, a soft muting circuitand a stereo noise control circuit.

The above described basic concept of the present invention can beapplied not only to a stereo demodulator circuit but also to all signalprocessing circuits performing some kind of signal processing.

That is, a signal processing circuit according to a first aspect of thepresent invention is characterized by a signal processing circuitcomprising at least one circuit part performing a prescribed controlresponding to an input signal level when the input signal level iswithin a specified range, and further comprising an AD converter unitfor AD-converting a level signal which is a signal indicating the inputsignal level; an offset unit for digitally offsetting a digital signalobtained from the AD converter unit by a predefined value according tothe specified range and truncating lower bits off the digital signal bythe number of bits specified in compliance with a grade of theprescribed control accuracy performed in the circuit part; and a controlsignal output unit for outputting a control signal defining a controlvariable of the prescribed control performed in the circuit part basedon a signal obtained from the offset unit.

Such a configuration of signal processing circuit enables a remarkablestabilization of control operations as with the above described stereodemodulator circuit according to the first aspect, and in addition, anefficient signal processing performed in the control signal output unit.

Meanwhile, a signal processing circuit according to a second aspect ofthe present invention is characterized by a signal processing circuitcomprising at least one circuit part performing a prescribed controlresponding to an input signal level when the input signal level iswithin a specified range, and further comprising an offset unit foroffsetting a level signal which is a signal indicating the input signallevel by a predefined value according to the specified range; adifference output unit for comparing a signal obtained from the offsetunit with a zero bias and outputting the resultant difference; and acontrol signal output unit for outputting a control signal defining acontrol variable of the prescribed control performed in the circuit partbased on a signal obtained from the difference output unit.

Such a configuration of signal processing circuit enables an accuratecontrol performed in the control circuit being unaffected by thetemperature changes, processing variations, etc., as with the stereodemodulator circuit according to the second aspect described above.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows a range of the RSSI in which each of processing, the HCC,SMUTE and SNC is performed;

FIG. 2 illustrates a circuit of an example of a conventional circuit (adifferential amplifier circuit) applied with a non-zero bias;

FIG. 3 shows a circuit of the stereo demodulator circuit 10 according toan embodiment of the present invention;

FIG. 4 shows a circuit of the control signal producing circuit 20 shownby FIG. 3;

FIG. 5 exemplifies an actual circuitry of the switch parts of thede-emphasis circuit 14 shown by FIG. 3; and

FIG. 6 shows a circuit of the differential amplifier circuit 30 adoptedfor a stereo demodulator circuit according to another embodiment of thepresent invention.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 3 shows a circuit of a stereo demodulator circuit 10 according toan embodiment of the present invention.

The stereo demodulator circuit 10 comprises, as a known configurationthereof, mainly a limiter/amplifier 11, an FM detection circuit 12, ahigh-cut control (“HCC” hereinafter) circuit 13, a de-emphasis circuit14, a soft muting (“SMUTE” hereinafter) circuit 15, a stereo noisecontrol (“SNC” hereinafter) circuit 16. In addition to the abovedescribed, the present embodiment further comprises an analog-to-digital(“A/D” hereinafter) converter 17, a latch circuit 18 and a controlsignal producing circuit 20. Note that the A/D converter 17 correspondsto the AD converter unit noted in the claims herein.

In the above configuration, an input signal (i.e., intermediatefrequency signal) Sig1 is inputted to the FM detection circuit 12 by wayof the limiter/amplifier 11, and a stereo composite signal is produced.Meanwhile, an RSSI signal Sig2 outputted from limiter/amplifier 11 isinputted to the A/D converter 17, as the AD converter unit, and therebythe analog RSSI signal Sig2 is converted to a digital signal Sig3. Theanalog-to-digital converted (“AD-converted” hereinafter) signal Sig3 istemporarily retained by the latch circuit 18 and then inputted to thecontrol signal producing circuit 20.

In the control signal producing circuit 20, a control signal controllingeach of a soft muting (SMUTE) processing by the SMUTE circuit 15, astereo noise control (SNC) processing by the SNC circuit 16 and ahigh-cut control (HCC) processing by the de-emphasis circuit 14 areproduced responding to the level of the inputted signal Sig3 (whichcorresponds to the RSSI).

FIG. 4 shows a circuit of the control signal producing circuit 20.

The control signal producing circuit 20 comprises three offset circuits21, 22 and 23, three selectors 24, 25 and 26 both disposed for theSMUTE, HCC and SNC processing, respectively, where the offset circuits21, 22 and 23 correspond to the offset units noted in the claims herein,and the selectors 24, 25 and 26 correspond to the control signal outputunits noted in the claims herein.

Here, the SMUTE circuit 15 performs the SMUTE processing responding tothe actual RSSI if the RSSI is within the predefined range (i.e., I₀˜I₁shown in FIG. 1), to the minimum value within the range (i.e., I₀ shownin FIG. 1) if the RSSI is smaller than the range, and to the maximumvalue within the range (i.e., I₁ shown in FIG. 1) if the RSSI is largerthan the range. Consequently, a digital value corresponding to theminimum value (i.e., I₀ shown in FIG. 1) within the range of the abovedescribed RSSI considered by the SMUTE circuit is set as an offset valueF₁ in the offset circuit 21 for such SMUTE circuit, and a digital signalSig3 responding to the RSSI is digitally offset by the above describedoffset value F₁. Then, a number of lower bits, by the number of bitsdetermined according to the grade of control accuracy required of theSMUTE circuit 15, are truncated from the signal obtained by the offsetdescribed above.

For example, let it be assumed that an actual original signal Sig3 ismade up by 5 bits, and a considerably coarser control accuracy is enoughfor the SMUTE circuit 15. In such a case, the signal Sig3 is firstoffset by the offset value F₁ responding to the minimum value I₀ withinthe range of the RSSI considered in the SMUTE processing, and forexample the lower two bits are truncated from the signal obtained by theoffset, and then only the remaining upper three bits will be outputted.The signal made up by the upper three bits thus truncated by two bitswill show a considerably coarser value than the actual RSSI value.

The offset circuit 22 disposed for the HCC and the offset circuit 23disposed for the SNC are approximately the same as the offset circuit 21disposed for the SMUTE. That is, they are configured as follows.

A digital value corresponding to the minimum RSSI value (i.e., I₂ shownin FIG. 1) within the range of the above described RSSI considered bythe HCC processing in the de-emphasis circuit 14 is set as an offsetvalue F₂ in the offset circuit 22 disposed for the HCC, and a digitalsignal Sig3 corresponding to the RSSI is digitally offset by the abovedescribed offset value F₂. Then, a number of lower bits, by the numberof bits determined in compliance with a grade of control accuracyrequired of the de-emphasis circuit 14, are truncated from the signalobtained by the offsetting described above.

For example, let it be assumed that an actual original signal Sig3 ismade up by 5 bits, and a little coarser control accuracy is enough forthe de-emphasis circuit 14. In such a case, the signal Sig3 is firstoffset by the offset value F₂ corresponding to the minimum value I₂within the range of the RSSI considered in the HCC processing, and forexample the lowest one bit is truncated from the signal obtained by theoffsetting, and then only the remaining upper four bits will beoutputted. The signal made up by the upper four bits thus truncated byone bit will show a little coarser value than the actual RSSI value.

A digital value corresponding to the minimum value (i.e., I₄ shown inFIG. 1) within the range of the above described RSSI considered by theSNC circuit 16 is set as an offset value F₃ in the offset circuit 23disposed for the SNC, and a digital signal Sig3 corresponding to theRSSI is digitally offset by the above described offset value F₃. Then, anumber of lower bits, by the number of bits determined in compliancewith a grade of control accuracy required of the SNC circuit 16, aretruncated from the signal obtained by the offsetting described above(naturally, there is no need to truncate if no coarser control ispreferred).

For example, let it be assumed that an actual original signal Sig3 ismade up by 5 bits, and relatively fine control accuracy is required ofthe SNC circuit 16. In such a case, the signal Sig3 is first offset bythe offset value F₃ corresponding to the minimum value I₄ within therange of the RSSI considered in the SNC processing, and no lower bit istruncated from the signal obtained by the offsetting, and then theoriginal five bits will be outputted. The signal made up by the fivebits without being truncated will show the same coarse value as theactual RSSI value.

As such, a signal made up by the number of bits in compliance with therespective control accuracy required for the SMUTE, HCC and SNC isoutputted from each of the three offset circuits 21, 22 and 23,respectively, with the number of these bits being proportionate with thecontrol accuracy. These offset circuits 21, 22 and 23 can actually beconfigured by the adders. That is, by retaining the negative value datarespectively corresponding to each of the offset values F₁, F₂ and F₃,and by adding it to the signal Sig3 each offset value is actuallysubtracted from the signal, Sig3. On sending out the data thus obtainedthrough the arithmetic operation, it is possible to truncate lowerdigits by devising so as not to send out those lower digits.

It goes without saying that other various methods are available fortruncating these bits while arbitrarily setting the number of bits to betruncated. The truncation can also be done by cutting the number of bitsoff the signal Sig3 prior to the offsetting.

And now, each of the selectors 24, 25 and 26 is equipped in thesubsequent stage of the offset circuits 21, 22 and 23, respectively, asshown by FIG. 4. These selectors 24, 25 and 26 are disposed foroutputting control signals in order to control the respective noisecontrol processing performed by the SMUTE circuit 15, de-emphasiscircuit 14 and SNC circuit 16, all shown by FIG. 3, stepwise in responseto the signal Sig4 (i.e., the signal obtained by the signal Sig3 offsetand the lower bits truncated), outputted from each of the offsetcircuits 21, 22 and 23.

For instance, the SNC circuit 16 shown in FIG. 3 comprises a pluralityof switches U₀, U₁, U₂ and U₃ disposed for changing resistanceincrementally responding to an RSSI in order to perform the SNCprocessing responding to the RSSI, by selecting the switch U₀ for areduced attenuation ratio of the L−R component, for example; orselecting U₁, U₂ or U₃, respectively and in this order, for anincrementally increased attenuation ratios. In this setup, the selector26 disposed for the SNC outputs a control signal to the SNC circuit 16instructing either one of the above described switches U₀, U₁, U₂ and U₃is to be selected according to the signal Sig4 outputted from the offsetcircuit 23. There, although the signal Sig4 indicates a negative valueif the RSSI is smaller than the predefined range (i.e., the range ofI₄˜I₅ shown in FIG. 1), a control signal will be outputted instructingto select the switch U₀ corresponding to the lowest limit I₄, while acontrol signal will be outputted instructing to select the switch U₃corresponding to the highest limit I₅, if the RSSI is larger than thepredefined range (i.e., the range of I₄˜I₅ shown in FIG. 1).

Note that control signals for the HCC and SMUTE processing arerespectively generated in the selector 25 disposed for the SNC and theselector 24 disposed for the SMUTE, as described thus far for theselector 26 disposed for the SNC.

For instance, in the case of the HCC processing performed in thede-emphasis circuit 14 (shown in FIG. 3), a control signal is outputtedfrom the selector 25 according to the signal Sig4 outputted from theoffset circuit 22 so as to select the switch S₀ for controlling toreduce the attenuation ratios of the L and R components, or one of theswitches S₁, S₂ or S₃, respectively and in this order, for controllingto increase the attenuation ratios thereof. Also in this case, if theRSSI is out of the specified range (i.e., the range of I₂˜I₃ shown inFIG. 1), a control signal is outputted instructing to select a switchcorresponding to either the lowest limit I₂ or the highest limit I₃, aswith the selector 26 disposed for the SNC.

Likewise, in the case of the SMUTE processing performed in the SMUTEcircuit 15 (shown in FIG. 3), a control signal is outputted from theselector 24 responding to the signal Sig4 outputted from the offsetcircuit 21 so as to select the switch V₀ for controlling to increase theattenuation ratio of the composite signal, or the switch V₁ forcontrolling to decrease the attenuation ratio thereof. Also in thiscase, if the RSSI is out of the specified range (i.e., the range ofI₀˜I₁ shown in FIG. 1), a control signal is outputted instructing toselect a switch corresponding to either the lowest limit I₀ or thehighest limit I₁ as with the selector 26 disposed for the SNC.

FIG. 5 exemplifies an actual circuitry of the switch parts of thede-emphasis circuit 14 shown by FIG. 3.

In FIG. 5, when the switch S₁ is selected, the signal outputted from thecontrol signal producing circuit 20 indicates S₀=off, S₁=on, S₂=off andS₃=off. When another of these switches is selected, the signal is suchthat only the signal inputted to the selected switch is set for “on” andthe others are set for “off.” Meanwhile, the similar switch parts forthe SMUTE circuit 15 and the SNC circuit 16 can be configured in thesame way as the switch part shown by FIG. 5 of the de-emphasis circuit14 shown by FIG. 3.

According to the present embodiment thus far described, smaller numbersof digits are required for processing by the selectors 24, 25 and 26 asa result of truncating the number of lower bits in compliance with therequired accuracy of each noise control and generating control signalsbased on the remaining upper bits in the selectors 24, 25 and 26, andhence an efficient signal processing is accomplished. Consequently, itis possible to configure the electors 24, 25 and 26 substantiallysimpler.

Note that, while the control signal producing circuit 20 is configuredby hardware comprising the offset circuits and the selectors in theabove described embodiment as shown in FIG. 4, a configuration thereofby a software operation is also possible. For example, the offsetcircuit 22 and the selector 25 disposed for the HCC exemplified abovecan be configured by software so that, first, a 4-bit signal isgenerated by truncating the lowest one bit from the 5-bit signal Sig3 incompliance with the required control accuracy of the HCC, and the offsetvalue F₂ (e.g., 3-bit value) is subtracted from the aforementioned 4-bitsignal. Then, if the subtraction result falls into a value correspondingto the range of the HCC, i.e., between I₂ and I₃ shown in FIG. 1 (e.g.,the decimal 0 through 7), a control signal is outputted instructing toturn on one of the switches (i.e., switches S₀ through S₃ shown in FIG.3) corresponding to the value, whereas if the above describedsubtraction result indicates a negative value, the same control signalas one corresponding to the result being “0” is outputted and if theabove described subtraction result indicates an “8” or greater, then thesame control signal as one corresponding to the result being “7” isoutputted. The above is merely an example, and the control signals forthe SMUTE and SNC can also be generated similarly according to thoseprocessing.

A stereo demodulator circuit according to the other embodiment of thepresent invention is then described as follows.

This embodiment premises a stereo demodulator circuit comprising atleast one of the noise control units (e.g., the de-emphasis circuit 14,the SMUTE circuit 15 and the SNC circuit 16 as shown in FIG. 3)controlling a noise responding to an RSSI when the RSSI is within aspecified range, and comprises a new control signal-producing circuit inplace of the control signal producing circuit 20 equipped in the stereodemodulator circuit 10 shown in FIG. 3. Let it be assumed here that thecontrol variable for a noise control in the above described noisecontrol units is determined by an analog control signal and thereforethe noise control units do not comprise a switch S, U or V as shown inFIG. 3.

Now, the above described unique control signal-producing circuitcomprises a not-shown offset circuit digitally offsetting a signal Sig3by a predefined value, i.e., the signal which has been A/D-converted bythe A/D converter 17 as shown in FIG. 3 and temporarily retained by thelatch circuit 18, a not-shown digital-to-analog (D/A) converterdigital-to-analog (D/A)-converting the offset signal and thedifferential amplifier circuit 30 amplifying the difference between theD/A-converted signal and the zero bias, and outputting it as the abovedescribed control signal.

While each of the offset circuits 21, 22 and 23 can be adopted as theabove described offset circuit, a function of truncating the lower bitsis optional. The above described D/A converter can be adopted from thewell known and therefore a description thereof is omitted herein.

In the above described differential amplifier circuit 30, which is adifferential amplifier circuit using a zero bias as the base voltage forcomparison as made apparent by FIG. 6, an analog signal (i.e., a signalresponding to an RSSI and already offset) obtained by D/A-conversion inthe above described D/A converter is inputted to the Vin terminal, theanalog signal is compared with the base voltage (i.e., zero volt) and anamplified difference between the above described two signals isoutputted. That is, since the point “b” is at the grounded zero bias,the difference between the already offset input signal into the Vinterminal and the zero bias at the point “b” is amplified and outputtedas a control signal to the above described noise control unit. In thiscase, the control signal is an analog signal, and hence the controlvariable for the above described noise control unit is continuouslychanged responding to the analog signal.

Such a configuration as above using the zero bias for the base voltageeliminates a fluctuation of the base voltage due to the temperaturechanges or processing variations, etc., thereby making the abovedescribed noise control unit perform a very precise noise control.

It shall be noted that the present invention is in no way limited tothese configurations put forth by the above described embodiments butcan be modified in various ways within the scope noted in each of theclaims herein.

APPLICABILITY TO USAGE IN INDUSTRIES

The technological concept of the present invention is applicable to notonly a stereo demodulator circuit but also various signal processingcircuits comprising at least one circuit part performing a prescribedcontrol according to an input signal level if the level is within apredefined range.

1. A stereo demodulator circuit comprising at least one noise controlunit for performing a noise control responding to a receptionelectric-field intensity when said reception electric-field intensity iswithin a specified range, further comprising: an AD converter unit forAD-converting a reception electric-field intensity signal indicatingsaid reception electric-field intensity; an offset unit for digitallyoffsetting a digital signal obtained from said AD converter unit by apredefined value according to said specified range and truncating lowerbits off said digital signal by the number of bits specified incompliance with a grade of noise control accuracy performed in saidnoise control unit; and a control signal output unit for outputting acontrol signal defining a control variable of a noise control performedin said noise control unit based on a signal obtained from said offsetunit.
 2. The stereo demodulator circuit in claim 1, wherein said noisecontrol unit is switched stepwise for providing a noise control variableresponding to a control signal outputted from said control signal outputunit.
 3. A stereo demodulator circuit comprising at least one noisecontrol unit for performing a noise control responding to a receptionelectric-field intensity when said reception electric-field intensity iswithin a specified range, further comprising: an offset unit foroffsetting a reception electric-field intensity signal indicating saidreception electric-field intensity by a predefined value according tosaid specified range; a difference output unit for comparing a signalobtained from said offset unit with a zero bias and outputting theresultant difference; and a control signal output unit for outputting acontrol signal defining a noise control variable for said noise controlunit based on a signal obtained from the difference output unit.
 4. Thestereo demodulator circuit in claim 1 further comprising a plurality ofsaid noise control units, wherein said specified range is respectivelyspecified for each of the plurality of noise control units.
 5. A signalprocessing circuit comprising at least one circuit part performing aprescribed control responding to an input signal level when said inputsignal level is within a specified range, further comprising: an ADconverter unit for AD-converting a level signal which is a signalindicating said input signal level; an offset unit for digitallyoffsetting a digital signal obtained from the AD converter unit by apredefined value according to said specified range and truncating lowerbits off said digital signal by the number of bits specified incompliance with a grade of said prescribed control accuracy performed insaid circuit part; and a control signal output unit for outputting acontrol signal defining a control variable of said prescribed controlperformed in said circuit part based on a signal obtained from theoffset unit.
 6. A signal processing circuit comprising at least onecircuit part performing a prescribed control responding to an inputsignal level when said input signal level is within a specified range,further comprising: an offset unit for offsetting a level signal whichis a signal indicating said input signal level by a predefined valueaccording to said specified range; a difference output unit forcomparing a signal obtained from the offset unit with a zero bias andoutputting the resultant difference; and a control signal output unitfor outputting a control signal defining a control variable of saidcontrol performed in said circuit part based on a signal obtained fromthe difference output unit.
 7. The stereo demodulator circuit in claim 3further comprising a plurality of said noise control units, wherein saidspecified range is respectively specified for each of the plurality ofnoise control units.